Electrical Engineering MCQ Question Papers: Campus Placement

Subject: Analog and Digital Electronics 4

**Part 4: List for questions and answers of Analog & Digital Electronics**

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**Q1.In NAND logic analysis procedure application used are of**

**a) Truth table**

**b) Feedback theorem**

**c) Demorgan’s theorem**

**d) K-map**

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**Q2.Circuits whose output depends on directly present input is called**

**a) Combinational circuit**

**b) Sequential circuit**

**c) Combinational sequence**

**d) Series**

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**Q3.Full subtract or is a**

**a) Combinational circuit**

**b) Sequential circuit**

**c) Combinational sequence**

**d) Series**

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**Q4.In first step of design procedure**

**a) Truth table is drawn**

**b) Circuit simplified**

**c) Circuit is drawn**

**d) Problem is stated**

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**Q5.Most significant bit of arithmetic addition is called**

**a) Overflow**

**b) Carry**

**c) Output**

**d) Zero bit**

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**Q6.Flip flop are constructed using**

**a) AND gate**

**b) OR gate**

**c) NAND gate**

**d) NOR gate **

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**Q7.Two bit addition is done by**

**a) Ripple carry adder**

**b) Carry sum adder**

**c) Full adder**

**d) Half adder**

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**Q8.AND gates are converted to NAND gates using**

**a) Invert OR**

**b) AND invert**

**c) NAND invert**

**d) Both a and b**

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**Q9.In map dont cares input are marked by**

**a) 0**

**b) 1**

**c) star**

**d) X**

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**Q10.Not operation is obtained by using one input**

**a) AND gate**

**b) OR gate**

**c) NAND gate**

**d) NOR gate**

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**Q11.Borrow in two bit (x,y) subtraction is 0, as long as**

**a) y greater than y**

**b) x equals to**

**c) x greater than equal to y**

**d) y greater than equal to x**

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**Q12.To check circuits as combinational not sequential is a analysis procedure’s**

**a) 1st step**

**b) 2nd step**

**c) 3rd step**

**d) 4th step**

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**Q13.Code not included in code conversion standard is**

**a) BCD code**

**b) Gray code**

**c) Excess3 code**

**d) Truth table **

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**Q14.OR gates are converted to NAND gates using**

**a) Invert OR**

**b) AND invert**

**c) NAND invert**

**d) both a and b**

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**Q15.To implement Boolean function with NAND gates we convert function to**

**a) AND logic**

**b) OR logic**

**c) NOR logic**

**d) NAND logic**

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**Q16.In real design procedure we consider**

**a) Max no of gates**

**b) Min no of gates**

**c) Two gates**

**d) Three gates**

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**Q17.Full adder performs addition on**

**a) 2 bits**

**b) 3 bits**

**c) 4 bits**

**d) 5 bits**

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**Q18.When both inputs are different output of xor is**

**a) 1**

**b) 0**

**c) x**

**d) 10**

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**Q19.Convenient way is to convert NAND logic diagram to its**

**a) AND diagram**

**b) OR diagram**

**c) AND-OR diagram**

**d) NOR diagram**

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**Q20.Result of two bit subtract or is called**

**a) Difference bit**

**b) Least significant bit**

**c) Most significant bit**

**d) Carry bit **

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**Part 4: List for questions and answers of Analog & Digital Electronics**

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**Q1. Answer:c**

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**Q2. Answer:a**

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**Q3. Answer:a**

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**Q4. Answer:d**

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**Q5. Answer:b**

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**Q6. Answer:c**

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**Q7. Answer:d**

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**Q8. Answer:b**

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**Q9. Answer:d**

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**Q10. Answer:c**

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**Q11. Answer:c**

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**Q12. Answer:a**

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**Q13. Answer:d**

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**Q14. Answer:a**

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**Q15. Answer:d**

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**Q16. Answer:b**

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**Q17. Answer:b**

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**Q18. Answer:a**

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**Q19. Answer:c**

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**Q20. Answer:a**