Computer Organization 1

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Electronic Engineering MCQ Question Papers: ENTC, IT Interview Placement

Subject: Computer Organization 1

Part 1: List for questions and answers of Computer Organization

 

Q1. The decoded instruction is stored in ______

a) IR

b) PC

c) Registers

d) MDR

 

Q2. The instruction -> Add LOCA,R0 does

a) Adds the value of LOCA to R0 and stores in the temp register

b) Adds the value of R0 to the address of LOCA

c) Adds the values of both LOCA and R0 and stores it in R0

d) Adds the value of LOCA with a value in accumulator and stores it in R0

 

Q3. Which registers can interact with the secondary storage ?

a) MAR

b) PC

c) IR

d) R0

 

Q4. During the execution of a program which gets initialized first ?

a) MDR

b) IR

c) PC

d) MAR

 

Q5. Which of the register/s of the processor is/are connected to Memory Bus ?

a) PC

b) MAR

c) IR

d) Both a and b

 

Q6. ISP stands for

a) Instruction Set Processor

b) Information Standard Processing

c) Interchange Standard Protocol

d) Interrupt Service Procedure 

 

Q7. The internal Components of the processor are connected by _______

a) Processor intra-connectivity circuitry

b) Processor bus

c) Memory bus

d) Rambus

 

Q8. ______ is used to choose between incrementing the PC or performing ALU operations

a) Conditional codes

b) Multiplexer

c) Control unit

d) None of these

 

Q9. The registers,ALU and the interconnection between them are collectively called as _____

a) Process route

b) Information trail

c) information path

d) data path

 

Q10. _______ is used to store data in registers

a) D flip flop

b) JK flip flop

c) RS flip flop

d) none of these

 

Q11. The instruction, Add #45,R1 does

a) Adds the value of 45 to the address of R1 and stores 45 in that address

b) Adds 45 to the value of R1 and stores it in R1

c) Finds the memory location 45 and adds that content to that of R1

d) None of the above

 

Q12. In case of, Zero-address instruction method the operands are stored in _____

a) Registers

b) Accumulators

c) Push down stack

d) Cache 

 

Q13. Add #45, when this instruction is executed the following happen/s

a) The processor raises an error and requests for one more operand

b) The value stored in memory location 45 is retrieved and one more operand is requested

c) The value 45 gets added to the value on the stack and is pushed onto the stack

d) None of these

 

Q14. The addressing mode which makes use of in-direction pointers is ______

a) Indirect addressing mode

b) Index addressing mode

c) Relative addressing mode

d) Offset addressing mode

 

Q15. In the following indexed addressing mode instruction, MOV 5(R1),LOC the effective address is ______

a) EA=5+R1

b) EA=R1

c) EA=[R1]

d) EA=5+[R1]

 

Q16. The addressing mode/s, which uses the PC instead of a general purpose register is ______

a) Indexed with offset

b) Relative

c) direct

d) both a and c

 

Q17. A collection of lines that connects several devices is called …………..

a) bus

b) peripheral connection wires

c) Both a and b

d) internal wires

 

Q18. The addressing mode, where you directly specify the operand value is _______

a) Immediate

b) Direct

c) Definite

d) Relative 

 

Q19. The effective address of the following instruction is , MUL 5(R1,R2)

a) 5+R1+R2

b) 5+(R1*R2)

c) 5+[R1]+[R2]

d) 5*([R1]+[R2])

 

Q20. _____ addressing mode is most suitable to change the normal sequence of execution of instructions

a) Relative

b) Indirect

c) Index with Offset

d) Immediate 

 

Part 1: List for questions and answers of Computer Organization


Q1. Answer: a

 

Q2. Answer: c

 

Q3. Answer: a

 

Q4. Answer: c

 

Q5. Answer: b

 

Q6. Answer: a

 

Q7. Answer: b

 

Q8. Answer: a

 

Q9. Answer: d

 

Q10. Answer: a

 

Q11. Answer: b

 

Q12. Answer: c

 

Q13. Answer: b

 

Q14. Answer: a

 

Q15. Answer: d

 

Q16. Answer: b

 

Q17. Answer: a

 

Q18. Answer: a

 

Q19. Answer: c

 

Q20. Answer: a