Microcontroller and Applications 1

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Electronic Engineering MCQ Question Papers: ENTC, IT Interview Placement

Subject: Microcontroller and Applications 1

Part 1: List for questions and answers of Microcontroller & Applications

 

Q1. Which flags of status register are most likely to get affected by the single-cycle increment and decrement instructions?

a) P Flags

b) C Flags

c) OV Flags

d) Z Flags

 

Q2. Where is the result stored after an execution of increment and decrement operations over the special – purpose registers in PIC?

a) File Register

b) Working Register

c) Both a & b

d) None of the above

 

Q3. Which instruction is applicable to set any bit while performing bitwise operation settings?

a) bcf

b) bsf

c) Both a & b

d) None of the above

 

Q4. What does the ‘program idata’ section of data memory contain in C-18 Compiler?

a) statically assigned/allocated initialized user variables

b) statically assigned /allocated uninitialized user variables

c) only executable instructions

d) variables as well as constants

 

Q5. In which aspects do the output functions specified in stdio.h differ from ANSI specified versions?

a) Provision of MPLAB specific extensions

b) Floating-point Format Support

c) Data in Program Memory

d) All of the above 

 

Q6. Which command-line option of compiler exhibits the banner comprising overall number of errors, messages, warnings and version number after an accomplishment of the compilation process?

a) help

b) verbose

c) overlay

d) char

 

Q7. Which among the below assertions represent the salient features of PIC in C-18 compiler?

a) Transparent read/ write access to an external memory

b) Provision of supporting an inline assembly during the necessity of an overall control

c) Integration with MPLAB IDE for source-level debugging

d) All of the above

 

Q8. Which register/s should set the SPEN bit in order to configure RC7/RX/DT pins as DT (data lines)?

a) TXSTA

b) RCSTA

c) Both a & b

d) None of the above

 

Q9. Which bit plays a salient role in defining the master or slave mode in TXSTA register especially in synchronous mode?

a) RSRC

b) CSRC

c) SPEN

d) SYNC

 

Q10. What is the status of shift clock supply in an USART synchronous mode?

a) Master-internally, Slave-externally

b) Master-externally, Slave-internally

c) Master & Slave (both) – internally

d) Master & Slave (both) – externally

 

Q11. How is the baud rate specified for high-speed (BRGH = 1) operation in an asynchronous mode?

a) FOSC / 8 (X + 1)

b) FOSC / 16 (X + 1)

c) FOSC / 32 (X + 1)

d) FOSC / 64 (X + 1) 

 

Q12. Why is the flag bit TXIF tested or examined in the PIR1 register after shifting all the data bits during the initialization process of USART in asynchronous mode?

a) For ensuring the transmission of byte

b) For ensuring the reception of byte

c) For ensuring the on-chip baud rate generation

d) For ensuring the 9th bit as a parity

 

Q13. What is the purpose of a special function register SPBRG in USART?

a) To control the operation associated with baud rate generation

b) To control an oscillator frequency

c) To control or prevent the false bit transmission of 9th bit

d) All of the above

 

Q14. Where should the value of TX9 bit be loaded during the 9 bit transmission in an asynchronous mode?

a) TXSTA

b) RCSTA

c) SPBRG

d) All of the above

 

Q15. How many upper bits of SSPSR are comparable to the address located in SSPADD especially after the shifting of 8 bits into SSPSR under the execution of START condition?

a) 7

b) 8

c) 16

d) 32

 

Q16. Where does the baud rate generation occur and begins to count the bits required to get transmitted, after an execution (set) of BF flag?

a) SCL line

b) SDA line

c) Both a & b

d) None of the above

 

Q17. Which command/s should be essentially written for I2C input threshold selection and slew rate control operations?

a) SSPSTAT

b) SSPIF

c) ACKSTAT

d) All of the above 

 

Q18. Which bits assist in determining the I2C bit rate during the initialization process of MSSP module in I2C mode?

a) SSPADD

b) SSPBUF

c) Both a & b

d) None of the above

 

Q19. What should be the value of SSPM3:SSPM0 bits so that SPI can enter the slave mode by enabling SS pin control?

a) 0000

b) 0100

c) 0010

d) 0001

 

Q20. Which bit of SSPCON must be necessarily set so as to enable the synchronization of serial port?

a) WCOL

b) SSPOV

c) CKP

d) SSPEN 

 

Part 1: List for questions and answers of Microcontroller & Applications

 

Q1. Answer: d

 

Q2. Answer: c

 

Q3. Answer: b

 

Q4. Answer: a

 

Q5. Answer: d

 

Q6. Answer: b

 

Q7. Answer: d

 

Q8. Answer: b

 

Q9. Answer: b

 

Q10. Answer: a

 

Q11. Answer: b

 

Q12. Answer: a

 

Q13. Answer: a

 

Q14. Answer: a

 

Q15. Answer: a

 

Q16. Answer: b

 

Q17. Answer: a

 

Q18. Answer: a

 

Q19. Answer: b

 

Q20. Answer: d