Electronic Engineering MCQ Question Papers: ENTC, IT Interview Placement
Subject: Microcontroller and Applications 2
Part 2: List for questions and answers of Microcontroller & Applications
Q1. Which among the below stated conditions are selected by the SSPCON & SSPSTAT control bits?
a) Slave Select mode in slave mode
b) Data input sample phase
c) Clock Rate in master mode
d) All of the above
Q2. Which among the below stated components should be filtered for determining the cutoff frequency corresponding to the PW period of low-pass filter?
a) Fundamental FPWM & higher harmonics
b) Resonant FPWM & higher harmonics
c) Slowly Varying DC components
d) Slowly Varying AC components
Q3. How do the variations in an average value get affected by PWM period?
a) Longer the PWM period, faster will be the variation in an average value
b) Shorter the PWM period, faster will be the variation in an average value
c) Shorter the PWM period, slower will be the variation in an average value
d) Longer the PWM period, slower will be the variation in an average value
Q4. What would be the resolution value if oscillator and PWM frequencies are 16MHz and 2 MHz respectively?
a) 2
b) 3
c) 4
d) 8
Q5. Why are the pulse width modulated outputs required in most of the applications?
a) To control average value of an input variables
b) To control average value of output variables
c) Both a & b
d) None of the above
Q6. Where does the comparison level occur for 16-bit contents in the compare mode operation?
a) Between CCPR1 register & TMR1
b) Between CCPR1 & CCPR2 registers
c) Between CCPR2 register & TMR1
d) Between CCPR2 register & TMR0
Q7. How does the pin RC2/CCP1 get configured while initializing the CCP module in the compare mode of operation?
a) As an input by writing it in TRISC register
b) As an output by writing it in TRISC register
c) As an input without the necessity of writing or specifying it in TRISC register
d) Compare mode does not support pin RC2/CCP1 configuration CCP initialization
Q8. What is the fundamental role exhibited by the CCP module in compare mode in addition to timer 1?
a) To vary the pin status in accordance to the precisely controlled time
b) To vary the duty cycle of the rectified output
c) To vary the oscillator frequencies in order to receive larger periods
d) To vary the status of synchronization levels
Q9. The capture operation in counter mode is feasible when mode of CCP module is _________
a) synchronized
b) asynchronized
c) synchronized as well as asynchronized
d) irrespective of synchronization
Q10. Which register is suitable for the corresponding count, if the measurement of pulse width is less than 65,535 μs along with the frequency of 4 MHz?
a) 4-bit register
b) 8-bit register
c) 16-bit register
d) 32-bit register
Q11. What happens when the program control enters the Interrupt Service Subroutine (ISS) due to enabling of CCP1IE bit in PIE1 especially during the initialization of CCP1 Module in capture mode?
a) CCP1F bit gets cleared in PIR1 by detecting new capture event
b) GIE bit gets enabled
c) Contents of CCPR1L & CCPR1H are automatically copied in TMR1L & TMR1H respectively
d) Interrupt flag bit CCP1IF gets enabled in PIR
Q12. What among the below specified functions is related to PWM mode?
a) Generation of an interrupt
b) Generation of rectangular wave with programmable duty cycle with an user assigned frequency
c) Variations in the status of an output pin
d) Detection of an exact point at which the change occurs in an input edge
Q13. Which mode allows to deliver the contents of 16-bit timer into a SFR on the basis of rising/falling edge detection?
a) Capture Mode
b) Compare Mode
c) PWM Mode
d) MSSP Mode
Q14. Which among the below mentioned aspect issues are supported by capture/compare/PWM modules corresponding to time in PIC 16F877?
a) Control
b) Measurement
c) Generation of pulse signal
d) All of the above
Q15. The functionalities associated with the pins RA0- RA3 in ADCON1 are manipulated by __________
a) PCFG1 & PCG0
b) VREF
c) ADON
d) All of the above
Q16. What would be the value of ADC clock source, if both the ADC clock bits are selected to be ‘1’?
a) FOSC/2
b) FOSC/8
c) FOSC/32
d) FRC
Q17. Which bit is mandatory to get initiated or set for executing the process of analog to digital conversion in ADCON0?
a) ADIF
b) ADON
c) Go/!Done
d) ADSC1
Q18. Which channel would be selected if the values of channel bits CHS0 & CHS1 are ‘1’ & ‘0’ respectively in ADC Status Register?
a) AIN0
b) AIN1
c) AIN2
d) AIN3
Q19. Which bits play a crucial role in specifying the details or reasons associated with the system wake-up in WDT?
a) PD & TO
b) C & Z
c) DC & RPO
d) All of the above
Q20. Which command enables the PIC to enter into the power down mode during the operation of watchdog timer (WDT)?
a) SLEEP
b) RESET
c) STATUS
d) CLR
Part 2: List for questions and answers of Microcontroller & Applications
Q1. Answer: d
Q2. Answer: a
Q3. Answer: b
Q4. Answer: b
Q5. Answer: b
Q6. Answer: c
Q7. Answer: b
Q8. Answer: a
Q9. Answer: a
Q10. Answer: c
Q11. Answer: a
Q12. Answer: b
Q13. Answer: a
Q14. Answer: d
Q15. Answer: a
Q16. Answer: d
Q17. Answer:
Q18. Answer: c
Q19. Answer: a
Q20. Answer: a