Microcontroller and Applications 3

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Electronic Engineering MCQ Question Papers: ENTC, IT Interview Placement

Subject: Microcontroller and Applications 3

Part 3: List for questions and answers of Microcontroller & Applications

 

Q1. How much delay is required to synchronize the external clock at TOCKI in Timer ‘0’ of PIC 16C61?

a) 2-cycles

b) 4-cycles

c) 6-cycles

d) 8-cycles

 

Q2. How much time is required for conversion per channel if PIC 16C71 possesses four analog channels, each comprising of 8-bits?

a) 10 µs

b) 15 µs

c) 20 µs

d) 30 µs

 

Q3. Where does the conversion interrupt flag (ADIF) end after an accomplishment of analog-to-digital (ADC) conversion process?

a) INTCON

b) ADCON0

c) OPTION

d) None of the above

 

Q4. What is the purpose of setting TOIE bit in INTCON along with GIE bit?

a) For setting the TOIF flag in INTCON due to generation of Timer 0 overflow interrupt

b) For setting the TOIE flag in INTCON due to generation of Timer 0 overflow interrupt

c) For setting the RBIF flag in INTCON due to generation of PORTB change interrupt

d) None of the above

 

Q5. Which bit-register pair plays a significant role in configuring the rising or falling edge triggering levels in external interrupts of PIC 16C61/71?

a) INTF bit – INTCON register

b) INTEDG bit – OPTION register

c) INT bit -INTCON register

d) INTE bit – OPTION register 

 

Q6. What kind of external edge-sensitive interrupt is generated due to transition effect at pin RBO/INT?

a) INT

b) RBO

c) INTF

d) All of the above

 

Q7. Which condition results in setting the GIE bit of INTCON automatically?

a) Execution of retfie instruction at the beginning of ISR

b) Execution of retfie instruction at the end of ISR

c) Execution of retfie instruction along with interrupt enable bit

d) Execution of retfie instruction along with interrupt disable bit

 

Q8. Which among the below specified combination of interrupts belong to the category of the PIC 16C61 / 71?

a) External, Timer/Counter & serial Port Interrupts

b) Internal, External & Timer/Counter Interrupts

c) External, Timer 0 & Port B Interrupts

d) Internal, External, Timer 0 & PortA Interrupts

 

Q9. What is the purpose of acquiring two different bits from INTCON register for performing any interrupt operation in PIC 16C61 / 71?

a) One for enabling & one for disabling the interrupt

b) One for enabling the interrupt & one for its occurrence detection

c) One for setting or clearing the RBIE bit

d) None of the above

 

Q10. A micro controller at-least should consist of:

a) RAM, ROM, I/O devices, serial and parallel ports and timers

b) CPU, RAM, I/O devices, serial and parallel ports and timers

c) CPU,RAM, ROM, I/O devices, serial and parallel ports and timers

d) CPU, ROM, I/O devices and timers

 

Q11. Which digital operations are performed over the detected mismatch outputs with an intention to generate a single output RB port change output?

a) OR

b) AND

c) EX-OR

d) NAND 

 

Q12. When does it become feasible for portB pins (RB4 to RB7) to support its unique feature of ‘interrupt on change’?

a) By configuring all the pins (RB4-RB7) as inputs

b) By configuring all the pins (RB4-RB7) as outputs

c) By configuring any one of the pins as inputs

d) By configuring any one of the pins as outputs

 

Q13. Which bit/s should be necessarily cleared in OPTION (SFR) register in order to turn on the weak internal pull-ups of port B?

a) RPO

b) RPBU

c) RBIF

d) All of the above

 

Q14. When does it become possible for a bit to get accessed from bank ‘0’ in the direct addressing mode of PICs?

a) Only when RPO bit is set ‘zero’

b) Only when RPO bit is set ‘1’

c) Only when RPO bit is utilized along with 7 lower bits of instruction code

d) Cannot Predict

 

Q15. Which bit permits to enable (if set) or disable (if cleared) all the interrupts in an INTCON register?

a) GIE

b) ADIE

c) RBIE

d) TOIE

 

Q16. Where is the exact specified location of an interrupt flag associated with analog-todigital converter?

a) INTCON

b) ADCON0

c) ADRES

d) PCLATH

 

Q17. Where are the prescalar assignments applied with a usage of PSA bit?

a) Only RTCC

b) Only Watchdog timer

c) Either RTCC or Watchdog timer

d) Neither RTCC nor Watchdog timer 

 

Q18. Which bit of OPTION register has a potential to decide the falling or rising edge sensitivity for the external interrupt INT?

a) RBPU

b) INTEDG

c) PSA

d) RTS

 

Q19. Which bank of RFS has a provision of addressing the status register?

a) Only Bank 1

b) Only Bank 2

c) Either Bank 1 or Bank 2

d) Neither Bank 1 nor Bank 2

 

Q20. Which register acts as an input-output control as well as data direction register for PORTA in bank 2 of RFS?

a) INDF (80H)

b) TRISB (85H)

c) TRISA (85H)

d) PCLATH (8A) 

 

Part 3: List for questions and answers of Microcontroller & Applications

 

Q1. Answer: a

 

Q2. Answer: c

 

Q3. Answer: b

 

Q4. Answer: a

 

Q5. Answer: b

 

Q6. Answer: a

 

Q7. Answer:

 

Q8. Answer: c

 

Q9. Answer: b

 

Q10. Answer: c

 

Q11. Answer: a

 

Q12. Answer: a

 

Q13. Answer: b

 

Q14. Answer: a

 

Q15. Answer: a

 

Q16. Answer: b

 

Q17. Answer: c

 

Q18. Answer: b

 

Q19. Answer: c

 

Q20. Answer: c