Electronic Engineering MCQ Question Papers: ENTC, IT Interview Placement
Subject: Microcontroller and Applications 6
Part 6: List for questions and answers of Microcontroller & Applications
Q1. Which pin/signal of ADC AD571 interfacing apprises about the accomplishment of data reading in the microcontroller so as to indicate ADC to get ready for the next data sample?
a) BLANK /CONVERT (high)
b) BLANK/DR (low)
c) DATA READY (DR)
d) Answer Explanation Related Ques
Q2. Which factors indicate the necessity of sample and hold circuit in the process of analogto-digital conversion?
a) Instantaneous variation in an input signal
b) Analog-to-digital conversion time
c) Both a & b
d) None of the above
Q3. Where do the power gets dissipated during the gradual decay of an inductor current (upto zero value) by turning OFF the transistor in an electromechanical relay?
a) Internal resistance of the coil
b) Internal Diode resistance
c) Both a & b
d) None of the above
Q4. Which diodes are employed in the electromechanical relays since the inductor current cannot be reduced to zero?
a) Tunnel Diode
b) Shockley Diode
c) Freewheeling Diode
d) Zener Diode
Q5. In an electromechanical relay, the necessity of connecting an external base resistance arises only _________
a) in the presence of an internal pull-up resistor
b) in the absence of an internal pull-up resistor
c) in the absence of an internal push-up resistor
d) in the presence of an internal push-up resistor
Q6. How is the latch interfacing with the microcontroller related to the number of digital output functions?
a) It increases the number of digital output functions in a time multiplexed manner
b) It decreases the number of digital output functions in a time multiplexed manner
c) It increases the number of digital output functions in a frequency multiplexed manner
d) It decreases the number of digital output functions in a frequency multiplexed manner
Q7. What happens when the latch is kept open once after the execution of the latch operation by allowing input digital data byte to appear at the output?
a) Variation in an input digital data
b) Output data remains constant despite changing input digital data
c) Variation in an output data with respect to input data variation
d) Cannot predict
Q8. Which ports assist in addressing lower order and higher address bytes into the data bus simultaneously, while accessing the external data memory?
a) Port 0 & Port 1 respectively
b) Port 1 & Port 2 respectively
c) Port 0 & Port 2 respectively
d) Port 2 & Port 3 respectively
Q9. Which among the below mentioned memory components possessess the potentiasignall of generating an ALE for the latching purpose of lower address byte in an external data memory?
a) CPU
b) Data Bus
c) Port 0
d) Port 1
Q10. What happens when the RD signal becomes low during the read cycle?
a) Data byte gets loaded from external data memory to data bus
b) Address byte gets loaded from external data memory to address bus
c) Data byte gets loaded from external program memory to data bus
d) Address byte gets loaded from external program memory to address bus
Q11. Which bus/es acquire/s the potential of liberally receiving the code byte after addressing the lower order address byte?
a) Data bus
b) Address bus
c) Both a & b
d) None of the above
Q12. Which essential operation should be performed while reading the external program byte on the data bus?
a) Latching of lower address byte
b) Latching of higher address byte
c) Latching of any addressable byte irrespective of priority level
d) None of the above
Q13. Which pin should be set low along with the program counter contents more than 0FFFH for accessing the external program memory?
a) EA
b) ALE
c) PSEN
d) All of the above
Q14. What value of ‘B’ should be loaded in the TRISB register if return lines (RB7:RB4) and RB3:RB0 are supposed to be inputs and outputs respectively after the PORT B initialization?
a) 11000100
b) 11110011
c) 11110001
d) 11110000
Q15. Which keys are encoded for scan lines with ‘1101’ value (RB1 low) condition?
a) 0, 4, 8, C
b) 1, 5, 9, D
c) 2, 6, A, E
d) 3, 7, B, F
Q16. Which lines are driven low under the software control during interfacing HEX keyboard with PIC 16F877?
a) Scan Lines
b) Return Lines
c) Both a & b
d) None of the above
Q17. What is the purpose of using Schmitt Trigger in the hardware circuit for key debouncing?
a) Noise Elimination
b) Improvement in Noise Immunity
c) Increase in Noise Figure
d) Reduction in Noise Temperature
Q18. Which is the an alternative mechanism of preventing the software to be dependent on several delay factors along with an optimum time proficiency of checking LCD status at the interfacing level?
a) Polling of DB7 bit of the data bus
b) Updating the faster display in less time
c) Generalization of clock frequency and display module
d) All of the above
Q19. How many data lines are essential in addition to RS, EN and RW control lines for interfacing LCD with Atmel 89C51 microcontroller?
a) 3
b) 5
c) 8
d) 10
Q20. How is the performance and the computer capability affected by increasing its internal bus width?
a) it increases and turns better
b) it decreases
c) remains the same
d) internal bus width don’t affect the performance in any way
Part 6: List for questions and answers of Microcontroller & Applications
Q1. Answer: a
Q2. Answer: c
Q3. Answer: c
Q4. Answer: c
Q5. Answer: b
Q6. Answer: a
Q7. Answer: b
Q8. Answer: c
Q9. Answer: a
Q10. Answer: a
Q11. Answer: a
Q12. Answer: a
Q13. Answer: a
Q14. Answer: d
Q15. Answer: c
Q16. Answer: a
Q17. Answer: b
Q18. Answer: a
Q19. Answer: c
Q20. Answer: a