VLSI Design and Technology 1

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Electronic Engineering MCQ Question Papers: ENTC, IT Interview Placement

Subject: VLSI Design and Technology 1

Part 1: List for questions and answers of VLSI Design and Technology

 

Q1. Which of the memory is volatile memory?

a) ROM

b) RAM

c) PROM

d) EEPROM

 

Q2. Which of following consume minimum power?

a) TTL

b) CMOS

c) DTL

d) RTL

 

Q3. Advantage(s) of an EEPROM over an EPROM is (are):

a) the EEPROM can erase and reprogram individual words without removal from the circuit

b) the EPROM can be erased with ultraviolet light in much less time than an EEPROM

c) the EEPROM has the ability to erase and reprogram individual words

d) the EEPROM can be erased and reprogrammed without removal from the circuit

 

Q4. An Assert is ______ command.

a) Sequential

b) Concurrent

c) Both a and b

d) None of the above

 

Q5. Leakage power is inversely proportional to _____________.

a) Options

b) Load Capacitance

c) Supply voltage

d) Threshold Voltage

 

Q6. Which among the following is pre-defined in the standard package as one-dimensional array type comprising each element of BIT type?

a) Bit type

b) Bit_vector type

c) Boolean type

d) All of the above 

 

Q7. Among the VHDL features, which language statements are executed at the same time in parallel flow?

a) Concurrent

b) Sequential

c) Net-list

d) Test-bench

 

Q8. Switch logic is based on?

a) pass transistor

b) inverters

c) gates

d) nmos gates

 

Q9. The number of gates that can be connected at the input ?

a) Fan IN

b) FAN OUT

c) D C FAN OUT

d) AC FANOUT

 

Q10. In VHDL, which object/s is/are used to connect entities together for the model formation?

a) Constant

b) Variable

c) Signal

d) All of the above

 

Q11. The yellow colour that is used in stickdiagram in NMOS design for?

a) N diffusion

b) Polysilicon

c) metal

d) metal

 

Q12. The level of any particular design can be measured by

a) SNR

b) Ratio of amplitude

c) Regularity

d) Quantity 

 

Q13. The Mead and Conway rules for tracks in the three nMOS conducting layers are

a) Minimum polysilicon width and seperation 2λ

b) Minimum diffusion width 2λ and seperation 3λ

c) Minimum metal width 3λ and seperation 3λ

d) All of the above

 

Q14. What programmable technology is used in FPGA devices?

a) SRAM

b) FLASH

c) Antifuse

d) All of the above

 

Q15. What are the kinds of subprograms

a) Functions

b) Procedures

c) Both a and b

d) None of the above

 

Q16. Capacitance of a MOS capacitor is

a) C0 =є0єins A

b) C0 =є0єins A /D

c) C0 =є0єins D/A

d) C0 =є0єins D/A

 

Q17. Test Access Port (TAP) Controller is a

a) 64-state finite state-machine

b) 32-state finite state-machine

c) 16-state finite state-machine

d) 8-state finite state-machine

 

Q18. Which configuration is more preferred duringfloorplaning

a) Double back with flipped rows

b) Double back with non flipped rows

c) With channel spacing between rows and no double back

d) With channel spacing between rows and double back 

 

Q19. The complex programmable logic device (CPLD) features a(n) ________ type of memory.

a) volatile

b) nonvolatile

c) EPROM

d) volitile EPROM

 

Q20. What are types of routing?

a) Global Routing

b) Track Assignment

c) Detail Routing

d) All of the above 

 

Part 1: List for questions and answers of VLSI Design and Technology

 

Q1. Answer: d

 

Q2. Answer: b

 

Q3. Answer: a

 

Q4. Answer: c

 

Q5. Answer: d

 

Q6. Answer: b

 

Q7. Answer: a

 

Q8. Answer: a

 

Q9. Answer: a

 

Q10. Answer: c

 

Q11. Answer: d

 

Q12. Answer: c

 

Q13. Answer: d

 

Q14. Answer: d

 

Q15. Answer: c

 

Q16. Answer: b

 

Q17. Answer: c

 

Q18. Answer: a

 

Q19. Answer: b

 

Q20. Answer: d