VLSI Design and Technology 2

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Electronic Engineering MCQ Question Papers: ENTC, IT Interview Placement

Subject: VLSI Design and Technology 2

Part 2: List for questions and answers of VLSI Design and Technology

 

Q1. Basically, an observability of an internal circuit node is a degree to which one can observe that node at the _______ of an integrated circuit

a) Inputs

b) Outputs

c) Both a and b

d) None of the above

 

Q2. High observability indicates that ________number of cycles are required to measure the output node value

a) More

b) Equal

c) Less

d) None of the above

 

Q3. Due to the limitations of the testers, the functional test is usually performed at speed _______the target speed

a) Lower than

b) Equal to

c) Greater than

d) None of the above

 

Q4. Which among the following is/are responsible for the occurrence of ‘Delay Faults’?

a) Variations in circuit delays and clock skews

b) Improper estimation of on-chip interconnect and routing delays

c) Aging effects and opens in metal lines connecting parallel transistors

d) All of the above

 

Q5. Which among the following serves as an input stage to most of the op-amps due to its compatibility with IC technology?

a) Differential amplifier

b) Cascode amplifier

c) Operational transconductance amplifiers (OTAs)

d) Voltage operational amplifier 

 

Q6. PSSR can be defined as the product of the ratio of change in supply voltage to change in output voltage of op-amp caused by the change in power supply and_______ of op-amp

a) Open-loop gain

b) Closed-loop gain

c) Both a and b

d) None of the above

 

Q7. According to the principle of current mirror, if gate-source potentials of two identical MOS transistors are equal, then the channel currents should be _______

a) Equal

b) Different

c) Both a and b

d) None of the above

 

Q8. In two-stage op-amp, what is the purpose of compensation circuitry?

a) To provide high gain

b) To lower output resistance and maintain large signal swing

c) To establish proper operating point for each transistor in its quiescent state

d) To achieve stable closed-loop performance

 

Q9. In accordance to the scaling technology, the total delay of the logic circuit depends on ______

a) The capacitor to be charged

b) The voltage through which capacitance must be charged

c) Available current

d) All of the above

 

Q10. In CMOS circuits, which type of power dissipation occurs due to switching of transient current and charging and discharging of load capacitance?

a) Static dissipation

b) Dynamic dissipation

c) Both a and b

d) None of the above

 

Q11. In high noise margin (NMH), the difference in magnitude between the maximum HIGH output voltage of driving gate and the maximum HIGH voltage is recognized by the _________gate

a) Driven

b) Receiving

c) Both a and b

d) None of the above 

 

Q12. Which factor/s play/s a crucial role in determining the speed of CMOS logic gate?

a) Load capacitance

b) Supply voltage

c) Gain factor of MOS

d) All of the above

 

Q13. The power consumption of static CMOS gates varies with the _____ of power supply voltage

a) square

b) cube

c) fourth power

d) 1/8 th power

 

Q14. In a chip, which type/s of pad design/s is/are adopted to solve the problem of pin count?

a) Input pad design

b) Output pad design

c) Three state pad design

d) All of the above

 

Q15. Maze routing is used to determine the _______path for a single wire between a set of points, if any path exists

a) Shortest

b) Average

c) Longest

d) None of the above

 

Q16. Maze routing is also known as ________

a) Viterbi’s algorithm

b) Lee/Moore algorithm

c) Prim’s algorithm

d) Quine-McCluskey algorithm

 

Q17. Which level of routing resources are supposed to be the dedicated lines allowing output of each tile to connect directly to every input of eight surrounding tiles?

a) Ultra-fast local resources

b) Efficient long-line resources

c) High speed, very long-line resources

d) High performance global networks 

 

Q18. In spartan-3 family architecture, which programmable functional element accepts two 18 bit binary numbers as inputs and computes the product?

a) Configurable Logic Blocks

b) Input Output Blocks

c) Block RAM

d) Multiplier Blocks

 

Q19. An antifuse element initial provides ______ between two conductors in absence of the application of sufficient programming voltage

a) Conduction

b) Insulation

c) Both a and b

d) None of the above

 

Q20. Which type of CPLD packaging comprises pins on all four sides that wrap around the edges of chip?

a) Plastic-Leaded Chip Carrier (PLCC)

b) Quad Flat Pack (QFP)

c) Ceramic Pin Grid Array (PGA)

d) Ball Grid Array (BGA) 

 

Part 2: List for questions and answers of VLSI Design and Technology

 

Q1. Answer: b

 

Q2. Answer: c

 

Q3. Answer: a

 

Q4. Answer: d

 

Q5. Answer: a

 

Q6. Answer: a

 

Q7. Answer: a

 

Q8. Answer: d

 

Q9. Answer: d

 

Q10. Answer: b

 

Q11. Answer: b

 

Q12. Answer: d

 

Q13. Answer: a

 

Q14. Answer: c

 

Q15. Answer: a

 

Q16. Answer: b

 

Q17. Answer: a

 

Q18. Answer: d

 

Q19. Answer: b

 

Q20. Answer: a