VLSI Design and Technology 3

COEP
Lets Crack Online Exam

Electronic Engineering MCQ Question Papers: ENTC, IT Interview Placement

Subject: VLSI Design and Technology 3

Part 3: List for questions and answers of VLSI Design and Technology

 

Q1. In Gray coding, when the state machine changes state, ______ bit/s in the state vector changes the value

a) one

b) two

c) four

d) eight

 

Q2. Which UART component/s divide/s the system clock to provide the bit clock with the period equal to one bit time and Bclock x 8?

a) Baud Rate Generator

b) Transmitter Section

c) Receiver Section

d) All of the above

 

Q3. If a port is declared as buffer, then which problem is generated in hierarchical design due to mapping with port of buffer mode of other entities only?

a) Structural Modeling

b) Functional Modeling

c) Behavioral Modeling

d) Data Flow Modeling

 

Q4. Why is the use of mode buffer prohibited in the design process of synthesizer?

a) To avoid mixing of clock edges

b) To prevent the occurrence of glitches and metastability

c) Because critical path has preference in placement

d) Because Maximum ASIC vendors fail to support mode buffer in libraries

 

Q5. What is/are the necessity/ies of Simulation Process in VHDL?

a) Requirement to test designs before implementation and usage

b) Reduction of development time

c) Decrease the time to market

d) All of the above

 

Q6. Timing analysis is more efficient with synchronous systems whose maximum operating frequency is evaluated by the _________path delay between consecutive flip-flops

a) shortest

b) average

c) longest

d) unpredictable 

 

Q7. An Assert is ______ command

a) Sequential

b) Concurrent

c) Both a and b

d) None of the above

 

Q8. The ‘next’ statements skip the remaining statement in the ________ iteration of loop and execution starts from first statement of next iteration of loop

a) Previous

b) Next

c) Current (present)

d) None of the above

 

Q9. Which among the following functions are performed by MSI category of IC technology?

a) Gates, Op-amps

b) Microprocessor/A/D

c) Filters

d) Memory/DSP

 

Q10. Which among the following EDA tool is available for design simulation?

a) CAD

b) ALDEC

c) Simucad

d) VIVElogic

 

Q11. Why is multiple stuck-at fault model preferred for DUT?

a) Because single stuck-at fault model is independent of design style and technology

b) Because single stuck-at tests cover major % of multiple stuck-at faults and unmodeled physical defects

c) Because complexity of test generation is reduced to greater extent in multiple stuckat fault models

d) All of the above

 

Q12. Which type/s of stuck at fault model exhibit/s the reduced complexity level of test generation?

a) Single

b) Multiple

c) Both a and b

d) None of the above 

 

Q13. Stuck open (off) fault occur/s due to _________

a) An incomplete contact (open) of source to drain node

b) Large separation of drain or source diffusion from the gate

c) Both a and b

d) None of the above

 

Q14. An ideal op-amp has ________

a) Infinite input resistance

b) Infinite differential voltage gain

c) Zero output resistance

d) All of the above

 

Q15. On the basis of an active load, which type of inverting CMOS amplifier represents low gain with highly predictable small and large signal characteristics?

a) Active PMOS load inverter

b) Current source load inverter

c) Push-pull inverter

d) None of the above

 

Q16. In MOS devices, the current at any instant of time is ______of the voltage across their terminals

a) constant and dependent

b) constant and independent

c) variable and dependent

d) variable and independent

 

Q17. For complex gate design in CMOS, OR function needs to be implemented by _______ connection/s of MOS

a) Series

b) Parallel

c) Both series and parallel

d) None of the above

 

Q18. In pull-up network, PMOS transistors of CMOS are connected in parallel with the provision of conducting path between output node and Vdd yielding _____ output

a) 1

b) 0

c) Both a and b

d) None of the above 

 

Q19. In CMOS inverter, the propagation delay of a gate is the/an _________ transition delay time for the signal during propagation from input to output especially when the signal changes its value

a) Highest

b) Average

c) Lowest

d) None of the above

 

Q20. In floorplanning, which phase/s play/s a crucial role in minimizing the ASIC area and the interconnection density?

a) Placement

b) Global Routing

c) Detailed Routing

d) All of the above 

 

Part 3: List for questions and answers of VLSI Design and Technology

 

Q1. Answer: a

 

Q2. Answer: a

 

Q3. Answer: a

 

Q4. Answer: d

 

Q5. Answer: d

 

Q6. Answer: c

 

Q7. Answer: c

 

Q8. Answer: c

 

Q9. Answer: c

 

Q10. Answer: d

 

Q11. Answer: d

 

Q12. Answer: b

 

Q13. Answer: c

 

Q14. Answer: d

 

Q15. Answer: a

 

Q16. Answer: b

 

Q17. Answer: b

 

Q18. Answer: a

 

Q19. Answer: b

 

Q20. Answer: a