VLSI Design and Technology 4

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Electronic Engineering MCQ Question Papers: ENTC, IT Interview Placement

Subject: VLSI Design and Technology 4

Part 4: List for questions and answers of VLSI Design and Technology

 

Q1. In floor planning, placement and routing are __________ tools

a) Front end

b) Back end

c) Both a and b

d) None of the above

 

Q2. In signal integrity, which noise/s occur/s due to impedance mismatch, stubs, vias and other interconnection discontinuities?

a) Power/Ground Noise

b) Crosstalk Noise

c) Reflection Noise

d) All of the above

 

Q3. Simple Programmable Logic Devices (SPLDs) are also regarded as _____________

a) Programmable Array Logic (PAL)

b) Generic Array Logic (GAL)

c) Programmable Logic Array (PLA)

d) All of the above

 

Q4. Which among the following is/are not suitable for in-system programming?

a) EPROM

b) EEPROM

c) Flash

d) All of the above

 

Q5. The devices which are based on fusible link or antifuse are _________time/s programmable

a) one

b) two

c) four

d) infinite

 

Q6. In SM chart for UART transmitter, which state/s indicate/s the waiting of sequential machine for the rising edge of bit clock and the consequent clearing of low order bit of TSR in order to transmit logic ‘0’ for one bit time?

a) IDLE State

b) Sync State

c) Transmit_Data_State

d) All of the above 

 

Q7. Which method/s is/are adopted for acquiring spike-free outputs?

a) Moore machine with clocked outputs

b) Mealy machine with clocked outputs

c) Output-state machine

d) All of the above

 

Q8. Which among the following is/are identical in Mealy and Moore machines?

a) Combinational output signal

b) Clocked Process

c) Both a and b

d) None of the above

 

Q9. Which among the following constraint/s is/are involved in a state-machine description?

a) State variable and clock

b) State transitions and output specifications

c) Reset condition

d) All of the above

 

Q10. If the level of fan-out is beyond a limit in synthesis, it results in an insertion of buffer by ultimate effect of _____ the speed

a) Enhancing

b) Reducing

c) Stabilizing

d) None of the above

 

Q11. In synthesis flow, which stage/s is/are responsible for converting an unoptimized boolean description to PLA format?

a) Translation

b) Optimization

c) Flattening

d) All of the above

 

Q12. Which among the following is/are regarded as the function/s of translation step in synthesis process?

a) Conversion of RTL description to boolean unoptimized description

b) Conversion of an unoptimized to optimized boolean description

c) Conversion of unoptimized boolean description to PLA format

d) All of the above 

 

Q13. Which functions are performed by static timing analysis in simulation?

a) Computation of delay for each timing path

b) Logic analysis in a static manner

c) Both a and b

d) None of the above

 

Q14. An event is nothing but ______ target signal, which is to be updated

a) Fixed

b) Change on

c) Both a and b

d) None of the above

 

Q15. Which concept proves to be beneficial in acquiring concurrency and order independence?

a) Alpha delay

b) Beta delay

c) Gamma delay

d) Delta delay

 

Q16. After an initialization phase, the simulator enters the ______phase

a) Compilation

b) Elaboration

c) Execution

d) None of the above

 

Q17. Which among the following wait statement execution causes the enclosing process to suspend and then wait for an event to occur on the signals?

a) Wait until Clk = ‘1’

b) Wait on x,y,z

c) Wait on clock until answer > 80

d) Wait for 12 ns

 

Q18. In composite data type of VHDL, the record type comprises the elements of _______data types

a) Same

b) Different

c) Both a and b

d) None of the above 

 

Q19. Which among the following is pre-defined in the standard package as one-dimensional array type comprising each element of BIT type?

a) Bit type

b) Bit_vector type

c) Boolean type

d) All of the above

 

Q20. In VHDL, which class of scalar data type represents the values necessary for a specific operation?

a) Integer types

b) Real types

c) Physical types

d) Enumerated types 

 

Part 4: List for questions and answers of VLSI Design and Technology

 

Q1. Answer: b

 

Q2. Answer: c

 

Q3. Answer: d

 

Q4. Answer: a

 

Q5. Answer: a

 

Q6. Answer: b

 

Q7. Answer: d

 

Q8. Answer: b

 

Q9. Answer: d

 

Q10. Answer: b

 

Q11. Answer: c

 

Q12. Answer: a

 

Q13. Answer: c

 

Q14. Answer: b

 

Q15. Answer: d

 

Q16. Answer: c

 

Q17. Answer: b

 

Q18. Answer: b

 

Q19. Answer: b

 

Q20. Answer: d