VLSI Design and Technology 5

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Electronic Engineering MCQ Question Papers: ENTC, IT Interview Placement

Subject: VLSI Design and Technology 5

Part 5: List for questions and answers of VLSI Design and Technology

 

Q1. Which among the following operation/s is/are executed in physical design or layout synthesis stage?

a) Placement of logic functions in optimized circuit in target chip

b) Interconnection of components in the chip

c) Both a and b

d) None of the above

 

Q2. Which among the following is/are taken into account for post-layout simulation?

a) Interconnect delays

b) Propagation delays

c) Logic cells

d) All of the above

 

Q3. Which level of system implementation includes the specific function oriented registers, counters and multiplexers?

a) Module level

b) Logical level

c) Physical level

d) All of the above

 

Q4. In logic synthesis, ________ is an EDIF that gives the description of logic cells and their interconnections

a) Netlist

b) Checklist

c) Shitlist

d) Dualist

 

Q5. Which among the following faults occur/s due to physical defects?

a) Process variations and abnormalities

b) Defects in silicon substrate

c) Photolithographic defects

d) All of the above

 

Q6. Which among the following is regarded as an electrical fault?

a) Excessive steady-state currents

b) Delay faults

c) Bridging faults

d) Logical stuck-at-0 or stuck-at-1 

 

Q7. In testability, which terminology is used to represent or indicate the formal evidences of correctness?

a) Validation

b) Verification

c) Simulation

d) Integration

 

Q8. Which among the following is/are regarded as an/the active resistor/s?

a) MOS diode

b) MOS transistor

c) MOS switch

d) All of the above

 

Q9. Which among the following can be regarded as an/the application/s of MOS switch in an IC design?

a) Multiplexing and Modulation

b) Transmission gate in digital circuits

c) Simulation of a resistor

d) All of the above

 

Q10. In DIBL, which among the following is/are regarded as the source/s of leakage?

a) ubthreshold conduction

b) Gate leakage

c) Junction leakage

d) All of the above

 

Q11. In enhancement MOSFET, the magnitude of output current __________ due to an increase in the magnitude of gate potentials

a) Increases

b) Remains constant

c) Decreases

d) None of the above

 

Q12. Which type of MOSFET exhibits no current at zero gate voltage?

a) Depletion MOSFET

b) Enhancement MOSFET

c) Both a and b

d) None of the above 

 

Q13. Increase in the physical distance of H-tree _________the skew rate

a) Increases

b) Stabilizes

c) Decreases

d) All of the above

 

Q14. Which method/s of physical clocking is/are a /the recursive structure where the memory elements are grouped together to make the use of nearby or same distribution points?

a) H tree

b) Balanced tree clock network

c) Both a and b

d) None of the above

 

Q15. Before the commencement of design, the clocking strategy determine/s __________

a) Number of clock signals necessary for routing throughout the chip

b) Number of transistors used per storage requirement

c) Power dissipated by chip and the size of chip

d) All of the above

 

Q16. Which programming technology/ies is/are predominantly associated with SPLDs and CPLDs?

a) EPROM

b) EEPROM

c) FLASH

d) All of the above

 

Q17. In fusible link technologies, the undesired fuses are removed by the pulse application of _____voltage and current to device input

a) Low

b) Moderate

c) High

d) All of the above

 

Q18. An Antifuse programming technology is predominantly associated with _____

a) SPLDs

b) FPGAs

c) CPLDs

d) All of the above 

 

Q19. Which of the following is not a basic element within the microprocessor?

a) Microcontroller

b) Arithmetic logic unit (ALU)

c) Register array

d) Control unit

 

Q20. Which method bypasses the CPU for certain types of data transfer?

a) Software interrupts

b) Interrupt-driven I/O

c) Polled I/O

d) Direct memory access (DMA) 

 

Part 5: List for questions and answers of VLSI Design and Technology

 

Q1. Answer: c

 

Q2. Answer: d

 

Q3. Answer: a

 

Q4. Answer: a

 

Q5. Answer: d

 

Q6. Answer: a

 

Q7. Answer: b

 

Q8. Answer: a

 

Q9. Answer: d

 

Q10. Answer: d

 

Q11. Answer: a

 

Q12. Answer: b

 

Q13. Answer: a

 

Q14. Answer: a

 

Q15. Answer: d

 

Q16. Answer: d

 

Q17. Answer: c

 

Q18. Answer: b

 

Q19. Answer: a

 

Q20. Answer: d