VLSI Design and Technology 6

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Electronic Engineering MCQ Question Papers: ENTC, IT Interview Placement

Subject: VLSI Design and Technology 6

Part 6: List for questions and answers of VLSI Design and Technology


Q1. Hold time is defined as the time required for the data to ________ after the triggering edge of clock

a) Increase

b) Decrease

c) Remain stable

d) All of the above


Q2. The time required for an input data to settle _____ the triggering edge of clock is known as ‘Setup Time’

a) Before

b) During

c) After

d) All of the above


Q3. The output of sequential circuit is regarded as a function of time sequence of __________

A. Inputs

B. Outputs

C. Internal States

D. External States

a) A and D

b) A and C

c) B and D

d) B and C


Q4. Which type of digital systems exhibit the necessity for the existence of at least one feedback path from output to input?

a) Combinational System

b) Sequential system

c) Both a and b

d) None of the above


Q5. Which attribute in synthesis process specify/ies the resistance by controlling the quantity of current it can source?

a) Load attribute

b) Drive attribute

c) Arrival time attribute

d) All of the above 


Q6. In synthesis process, the load attribute specify/ies the existing amount of _________load on a particular output signal

a) Inductive

b) Resistive

c) Capacitive

d) All of the above


Q7. Register transfer level description specifies all of the registers in a design and ______ logic between them

a) Sequential

b) Combinational

c) Both a and b

d) None of the above


Q8. Which among the following is an output generated by synthesis process?

a) Attributes and Library

b) RTL VHDL description

c) Circuit constraints

d) Gate-level net list


Q9. Which among the following is not a characteristic of ‘Event-driven Simulator’?

a) Identification of timing violations

b) Storage of state values and time information

c) Time delay calculation

d) No event scheduling


Q10. Which type of simulator/s neglect/s the intra-cycle state transitions by checking the status of target signals periodically irrespective of any events?

a) Event-driven Simulator

b) Cycle-based Simulator

c) Both a and b

d) None of the above


Q11. In the simulation process, which step specifies the conversion of VHDL intermediate code so that it can be used by the simulator?

a) Compilation

b) Elaboration

c) Initialization

d) Execution 


Q12. Which type of simulation mode is used to check the timing performance of a design?

a) Behavioural

b) Switch-level

c) Transistor-level

d) Gate-level


Q13. Which data type in VHDL is non synthesizable and allows the designer to model the objects of dynamic nature?

a) Scalar

b) Access

c) Composite

d) File


Q14. In VHDL, which object/s is/are used to connect entities together for the model formation?

a) Constant

b) Variable

c) Signal

d) All of the above


Q15. In Net-list language, the net-list is generated _______synthesizing VHDL code

a) Before

b) At the time of (during)

c) After

d) None of the above


Q16. Among the VHDL features, which language statements are executed at the same time in parallel flow?

a) Concurrent

b) Sequential

c) Net-list

d) Test-bench


Q17. In VLSI design, which process deals with the determination of resistance and capacitance of interconnections?

a) Floor planning

b) Placement and Routing

c) Testing

d) Extraction 


Q18. _________ is the fundamental architecture block or element of a target PLD

a) System Partitioning

b) Pre-layout Simulation

c) Logic cell

d) Post-layout Simulation


Q19. Which among the following is a process of transforming design entry information of the circuit into a set of logic equations?

a) Simulation

b) Optimization

c) Synthesis

d) Verification


Q20. The utilization of CAD tools for drawing timing waveform diagram and transforming it into a network of logic gates is known as _______

a) Waveform Editor

b) Waveform Estimator

c) Waveform Simulator

d) Waveform Evaluator 


Part 6: List for questions and answers of VLSI Design and Technology


Q1. Answer: c


Q2. Answer: a


Q3. Answer: b


Q4. Answer: b


Q5. Answer: b


Q6. Answer: c


Q7. Answer: b


Q8. Answer: d


Q9. Answer: d


Q10. Answer: b


Q11. Answer: b


Q12. Answer: d


Q13. Answer: b


Q14. Answer: c


Q15. Answer: c


Q16. Answer: a


Q17. Answer: d


Q18. Answer: c


Q19. Answer: c


Q20. Answer: a